`timescale 1ns/1ns
`define k 256
`define m 16

module Register_ModOp(input clk,
					input rst_n,
					input curve_sel,
					input mod,
					//input [`k-1:0] p,
					input [`k+`m+2:0] s_in_m,
					input [`k+`m+2:0] s_in_a,
					input [`k+`m+2:0] c_in_m,
					input [`k+`m+2:0] c_in_a,
					input [`k:0] u_in,
					//input [`k:0] v_in,
					input [`k-1:0] v_in,
					input [`k-1:0] a,//连到外部a
					input [8:0] r_sel,//S、C、U、V输入选择
					output reg [`k+`m+2:0] s_out,
					output reg [`k+`m+2:0] c_out,
					output reg [`k:0] u_out,
					//output reg [`k:0] v_out
					output reg [`k-1:0] v_out
				   );
				   
always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		s_out <= 275'b0;
	end
	else
	begin
		case(r_sel[1:0])
			2'b01 : s_out <= s_in_m;
			2'b10 : s_out <= s_in_a;
			2'b11 : s_out <= 275'b0;
			default : s_out <= s_out;
		endcase
	end
end

always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		c_out <= 275'b0;
	end
	else
	begin
		case(r_sel[4:2])
			3'b001 : c_out <= c_in_m;
			3'b010 : c_out <= c_in_a;
			3'b011 : c_out <= 275'd1;
			3'b111 : c_out <= 275'b0;
			default : c_out <= c_out;
		endcase
	end
end

always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		u_out <= 256'b0;
	end
	else
	begin
		case(r_sel[6:5])
			2'b01 : u_out <= u_in;
			2'b11 : if(curve_sel == 1'b0)
						if(mod == 1'b0)
							u_out <= ~(256'hffffffff00000001000000000000000000000000ffffffffffffffffffffffff)+1;
						else
							u_out <= ~(256'hFFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551)+1;
					else
						if(mod == 1'b0)
							u_out <= ~(256'hFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF00000000FFFFFFFFFFFFFFFF)+1;
						else
							u_out <= ~(256'hFFFFFFFEFFFFFFFFFFFFFFFFFFFFFFFF7203DF6B21C6052B53BBF40939D54123)+1;
			//2'b10 : u_out <= 256'b0;
			default : u_out <= u_out;
		endcase
	end
end

always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
	begin
		v_out <= 256'b0;
	end
	else
	begin
		case(r_sel[8:7])
			2'b01 : v_out <= v_in;
			2'b11 : v_out <= a;
			//2'b10 : v_out <= 256'b0;
			default : v_out <= v_out;
		endcase
	end
end

endmodule